1. Field of the Invention
The present invention relates to a buffer and an organic light emitting display using the buffer, and more particularly to a buffer and an organic light emitting display using the buffer, which is configured of p-channel metal-oxide-semiconductor (PMOS) transistors to be capable of preventing leakage current.
2. Description of the Related Art
Recently, various flat panel display devices capable of reducing weight and volume, overcoming the disadvantages of a cathode ray tube, have been developed. Among the flat panel display devices, there are liquid crystal displays, field emission displays, plasma display panels, and organic light emitting displays.
The organic light emitting display displays an image through an organic light emitting diode (OLED) that generates light by re-coupling electrons and holes. The organic light emitting display is advantageous in having rapid response speed as well as low power consumption.
The organic light emitting display includes a plurality of pixels arranged in a two-dimensional array, a data driver for supplying data signals to data lines connected to the pixels, and a scan driver for supplying scan signals to scan lines connected to the pixels.
The data driver allows a predetermined image to be displayed on the pixels by supplying data signals that have information of data in every time period. The scan driver selects pixels, on which the data signals are to be supplied, by sequentially supplying scan signals in every time period.
As the panel size of the organic light emitting display becomes large, the data driver and/or the scan driver should be mounted on the panel in order to reduce size, weight, and manufacturing costs of the organic light emitting display. The buffer installed in a contemporary data driver and/or scan driver, however, is configured of both of p-channel metal-oxide-semiconductor (PMOS) transistors and n-channel metal-oxide-semiconductor (NMOS) transistors. Therefore, it is difficult to mount two different types of semiconductors on the panel, because PMOS and NMOS transistors cannot be manufactured at the same time. Accordingly additional manufacturing processes are necessary and manufacturing cost increases.
FIG. 1 is a diagram showing a buffer that can be installed in a contemporary data driver and/or scan driver. Referring to FIG. 1, the buffer includes first transistor M1 and third transistor M3 connected between first power source VDD and second power source VSS, and second transistor M2 and forth transistor M4 connected between first power source VDD and second power source VSS. The voltage of first power source VDD is set to be higher than the voltage of second power source VSS.
Gate electrodes of first transistor M1 and third transistor M3 are connected to input terminal IN. And, a first electrode of first transistor M1 is connected to first power source VDD, and a first electrode of third transistor M3 is connected to second power source VSS. A second electrode of first transistor M1 and a second electrode of third transistor M3 are connected to gate electrodes of second transistor M2 and fourth transistor M4. Herein, each of a first electrode and a second electrode of a transistor can be a source electrode or a drain electrode. For example, if a first electrode of a transistor is a source electrode, then a second electrode of the transistor is a drain electrode. Alternatively, a first electrode can be a drain electrode and a second electrode can be a source electrode.
The first electrode of second transistor M2 is connected to first power source VDD, and the first electrode of fourth transistor M4 is connected to second power source VSS. The second electrode of second transistor M2 and the second electrode of fourth transistor M4 are connected to output terminal OUT.
Describing operation processes, two types of signals (a low signal and a high signal) can be applied to input terminal IN. A low signal turns on transistors M1 and M2. Transistors M3 and M4 are different type from transistor M1 and M2, and a high signal turns on transistors M3 and M4. If a low signal is inputted to input terminal IN, first transistor M1 is turned on. If first transistor M1 is turned on, voltage of first power source VDD, which is a high signal, is supplied to both of the gate electrodes of second transistor M2 and fourth transistor M4. Therefore, fourth transistor M4 is turned on. Then, the voltage of second power source VSS is outputted through output terminal OUT. In other words, when a low signal is inputted to input terminal IN, the voltage of second power source VSS is outputted through output terminal OUT.
If a high signal is inputted to input terminal IN, third transistor M3 is turned on. If third transistor M3 is turned on, voltage of second power source VSS, which is a low signal, is supplied to both of the gate electrodes of second transistor M2 and fourth transistor M4. Therefore second transistor M2 is turned on. Then, the voltage of first power source VDD is outputted through output terminal OUT. In other words, if a high signal is inputted to input terminal IN, the voltage of first power source VDD is outputted through output terminal OUT.
However, this buffer is configured of NMOS transistors M3 and M4, and PMOS transistors M1 and M2, and therefore it is difficult to mount both of NMOS and PMOS transistors on a display panel.